PDP83TG720SWCSTQ1 datasheet(66/199 Pages) TI

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7.6.2.10 MII_REG_16 Register (Address = 0x16) [reset = 0x0]

MII_REG_16 is shown in Table 7-33.

Return to the Summary Table.

Table 7-33. MII_REG_16 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

RESERVED

5b00000

Reserved

prbs_sync_loss

R/W0C

1b0

Prbs lock lost latch status

1b0 = Prbs lock never lost

1b1 = Prbs lock had been lost

RESERVED

1b0

Reserved

core_pwr_mode

1b0

1b = Core is is normal power mode 0b = Core is in power down or

sleep mode

1b0 = Core is in power down or sleep mode

1b1 = Core is is normal power mode

cfg_dig_pcs_loopback

R/W

1b0

PCS digital loopback

6-0

loopback_mode

R/W

7b0000000

Bits[4:0]: 000001b = PCS loop 000010b = RS loop 000100b = Digital

loop 001000b = Analog loop 010000b = Reverse loop Bit[5] (should

be set only in reverse loop) 1 = Transmit data to MAC in reverse loop

0 = Suppress data to MAC in reverse loop Bit[6] (should be set only

in MII loop) 1 = Transmit data to MDI in MII loop 0 = Suppress data

to MDI in MII loop

7b0000001 = PCS loop

7b0000010 = RS loop

7b0000100 = Digital loop

7b0010000 = Reverse loop

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

www.ti.com

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