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PDP83TG720SWCSTQ1 Datasheet(PDF) 98 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 98 Page - Texas Instruments |
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98 / 199 page ![]() 7.6.2.42 TEST_MODE Register (Address = 0x531) [reset = 0x0] TEST_MODE is shown in Table 7-65. Return to the Summary Table. Table 7-65. TEST_MODE Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 7b0000000 Reserved 8 cfg_test_mode4_tx_order R/W 1b0 Order of symbols to be transmitted in Test mode 4 1b0 = T1 followed by T2 1b1 = T2 followed by T1 7-0 cfg_test_mode_7_data R/W 8b00000000 GMII data to transmit in Test mode 7 DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 98 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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