Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

PDP83TG720SWCSTQ1 Datasheet(PDF) 15 Page - Texas Instruments

Part # PDP83TG720SWCSTQ1
Description  DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY
PDF  199 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PDP83TG720SWCSTQ1 Datasheet(HTML) 15 Page - Texas Instruments

Back Button PDP83TG720SWCSTQ1 Datasheet HTML 11Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 12Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 13Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 14Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 15Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 16Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 17Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 18Page - Texas Instruments PDP83TG720SWCSTQ1 Datasheet HTML 19Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 199 page
background image
(1)
PARAMETER
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
Tfall
Vod Fall Time
100
200
ps
Jitter
Output jitter
300
ps
25 MHz CRYSTAL REQUIREMENTS
Frequency
25
MHz
Frequency Tolerance and Stability Over temperature and aging
–100
100
ppm
Equivalent Series Resistance
50
Ω
OUTPUT CLOCK TIMING (CLKOUT)
Frequency
25
MHz
Duty Cycle ( With XI source as 50%)
48
52
%
Rise / Fall Time (10% - 90%)
2.5
ns
Jitter (RMS) (Slave Mode, MAC Iinterface : SGMII)
3.6
ps
Jitter (RMS) (Master Mode, MAC Iinterface : SGMII)
2.4
ps
Jitter (RMS) (Slave Mode, MAC Interface : RGMII)
11
ps
Jitter (RMS) (Master Mode, MAC Interface : RGMII)
15
ps
Sleep Entry and Wake-Up
MDI Energy Loss to Sleep Entry; INH Transition LOW
Normal Mode,
WAKE = LOW,
sleep_en = TRUE
4
ms
Local Wake-Up Pulse Duration
Sleep Mode, WAKE
pin
48
80
µs
MDI Energy Detection Wake-Up Pulse Duration
Sleep Mode
0.75
1.25
ms
(1)
Ensured by production test or characterization or design.
(2)
No supply sequencing constraint across power rails
(3)
In case OSC clock is delayed, additional reset is needed post Osc clock stablisation
(4)
Refer register[0x0430] for programmability of RX delay codes
(5)
PHY provides internal delays on TX_CLK to TX_D[3:0] to add additional skew upto 2 ns. Refer to register[0x0430] for programmability
www.ti.com
DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com