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PDP83TG720SWCSTQ1 Datasheet(PDF) 81 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 199 page ![]() 7.6.2.25 TDR_CFG2 Register (Address = 0x303) [reset = 0x172D] TDR_CFG2 is shown in Table 7-48. Return to the Summary Table. Table 7-48. TDR_CFG2 Register Field Descriptions Bit Field Type Reset Description 15-8 cfg_tdr_flt_loc_offset R/W 8b00010111 tap index offset of dyamic peak equation 7-0 cfg_tdr_flt_init R/W 8b00101101 Offset of dynamic peak equation www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 81 |
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