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PDP83TG720SWCSTQ1 Datasheet(PDF) 38 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 199 page ![]() accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to sample the control signal pin on transmit and receive paths. For 1-Gbps operation, RX_CLK and TX_CLK operate at 125 MHz. The RGMII signals are summarized in Table 7-8: Table 7-8. RGMII Signals FUNCTION PINS Data Signals TX_D[3:0] RX_D[3:0] Control Signals TX_CTRL RX_CTRL Clock Signals TX_CLK RX_CLK PHY MAC TX_CLK TX_CTRL TX_D[3:0] RX_CLK RX_CTRL RX_D[3:0] 25-MHz Crystal or CMOS-level Oscillator Figure 7-14. RGMII Connections DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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