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PDP83TG720SWCSTQ1 Datasheet(PDF) 71 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 199 page  7.6.2.15 C_AND_S_STATUS Register (Address = 0x180) [reset = 0x0] C_AND_S_STATUS is shown in Table 7-38. Return to the Summary Table. Table 7-38. C_AND_S_STATUS Register Field Descriptions Bit Field Type Reset Description 15 link_up R 1b0 link up defined by CnS 14 link_down R 1b0 link down as defined by CnS 13 phy_ctrl_send_data R 1b0 phy control in send data status 12 link_status R 1b0 link status 11-8 pm_coded_state R 4b0000 pm state 7 sel_osc25_clk_n R 1b0 25MHz clock select 6 pll_clk_sel R 1b0 Pll clock select 5 pwr_seq_done R 1b0 Power seq done status 4 slave_ph1_done R 1b0 slave ph1 done status 3 channel_ok R 1b0 channel okay status 2 descr_sync R 1b0 Descrambler lock status 1 loc_rcvr_status R 1b0 Local receiver status 0 rem_rcvr_status R 1b0 Remote receiver status www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 71 |
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