PDP83TG720SWCSTQ1 datasheet(61/199 Pages) TI

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7.6.2.5 MII_REG_F Register (Address = 0xF) [reset = 0x0]

MII_REG_F is shown in Table 7-28.

Return to the Summary Table.

Table 7-28. MII_REG_F Register Field Descriptions

Bit

Field

Type

Reset

Description

ieee_1000basex_fd

1b0

1 = PHY able to perform full duplex 1000BASE-X 0 = PHY not able

to perform full duplex 1000BASE-X

1b0 = PHY not able to perform full duplex 1000BASE-X

1b1 = PHY able to perform full duplex 1000BASE-X

ieee_1000basex_hd

1b0

1 = PHY able to perform half duplex 1000BASE-X 0 = PHY not able

to perform half duplex 1000BASE-X

1b0 = PHY not able to perform half duplex 1000BASE-X

1b1 = PHY able to perform half duplex 1000BASE-X

ieee_1000baset_fd

1b0

1 = PHY able to perform full duplex 1000BASE-T 0 = PHY not able

to perform full duplex 1000BASE-T

1b0 = PHY not able to perform full duplex 1000BASE-T

1b1 = PHY able to perform full duplex 1000BASE-T

ieee_1000baset_hd

1b0

1 = PHY able to perform half duplex 1000BASE-T 0 = PHY not able

to perform half duplex 1000BASE-T

1b0 = PHY not able to perform half duplex 1000BASE-T

1b1 = PHY able to perform half duplex 1000BASE-T

11-0

RESERVED

12b0000000

00000

Reserved

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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PDP83TG720SWCSTQ1 Datasheet(PDF) 61 Page - Texas Instruments

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