PDP83TG720SWCSTQ1 datasheet(34/199 Pages) TI

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7.4 Device Functional Modes

Normal

PHY Enabled

Sleep

Power-off

PHY Disabled

State

Change #2

State

Change #1

RESET_N = HIGH

and

POR = complete

Power-on

Power-off

State Change #4

Standby

PHY Disabled

RESET_N = LOW

and Power-on

From any state

State Change #3

Standby/Normal

Reset

PHY Disabled

Figure 7-12. PHY Operation State Diagram

7.4.1 Power Down

When VDDA3P3 or VDDIO or VDD1P0 is below the POR threshold, the DP83TG720S-Q1 is in a power-down

state. All digital IOs will remain in high impedance state and analog blocks are disabled. PMA termination is not

present when in power-down.

7.4.2 Reset

Reset is activated upon power-up, when RESET_N is pulled LOW (for the minimum reset pulse time) or if

hardware reset is initiated by setting bit[15] in the register[0x001F].

• Digital state machine restarts after reset and all the register settings are cleared to the boot-up state.

• 25MHz clock on clkout pin will remain active during reset state also.

• MDI/PMA will not have termination during reset state.

Note

Straps are re-latched only with pin reset and not by hardware reset through register (register

[0x001F] = x8000.

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

www.ti.com

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