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PDP83TG720SWCSTQ1 Datasheet(PDF) 84 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 199 page ![]() 7.6.2.28 TDR_STATUS0 Register (Address = 0x309) [reset = 0x0] TDR_STATUS0 is shown in Table 7-51. Return to the Summary Table. Table 7-51. TDR_STATUS0 Register Field Descriptions Bit Field Type Reset Description 15-8 peak1_loc R 8b00000000 Peak 1 location in tap index 7-0 peak0_loc R 8b00000000 Peak 0 location in tap index DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 84 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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