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PDP83TG720SWCSTQ1 Datasheet(PDF) 56 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 199 page  7.6.2.1 BMCR Register (Address = 0x0) [reset = 0x140] BMCR is shown in Table 7-24. Return to the Summary Table. Table 7-24. BMCR Register Field Descriptions Bit Field Type Reset Description 15 mii_reset R/WMC 1b0 MII Reset 1b0 = No reset 1b1 = Digital in reset and all MII regs (0x0 - 0xF) reset to default 14 loopback R/W 1b0 MII loopback enable 1b0 = No MII loopback 1b1 = MII loopback 13 speed_sel_lsb R 1b0 Speed selection LSB 1b0 = 10 Mb/s 1b1 = 100 Mb/s 1b10 = 1000 Mb/s 1b11 = Reserved 12 mr_an_enable R 1b0 Reserved 11 power_down R/W 1b0 Power down mode enable 1b0 = Normal mode 1b1 = Power down via register or pin 10 isolate R/W 1b0 Isolate mode enable 1b0 = Normal mode 1b1 = Isolate mode 9 mr_restart_an R 1b0 Reserved 8 duplex_mode R 1b1 Duplex mode 1b0 = Half duplex 1b1 = Full duplex 7 col_test R 1b0 Reserved 6 speed_sel_msb R 1b1 Speed selection MSB 1b0 = 10 Mb/s 1b1 = 100 Mb/s 1b10 = 1000 Mb/s 1b11 = Reserved 5 unidirectional_ability R 1b0 Reserved 4-0 RESERVED R 5b00000 Reserved DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 56 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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