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PDP83TG720SWCSTQ1 Datasheet(PDF) 101 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 101 Page - Texas Instruments |
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101 / 199 page  7.6.2.45 LINK_DOWN_LATCH_STAT Register (Address = 0x545) [reset = 0x0] LINK_DOWN_LATCH_STAT is shown in Table 7-68. Return to the Summary Table. Table 7-68. LINK_DOWN_LATCH_STAT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 10b0000000 000 Reserved 5 channel_ok_ll R/W0C 1b0 Channel ok latch low indication 1b0 = Channel ok was de-asserted 1b1 = Channel ok was never de-asserted 4 link_fail_inhibit_lh R/W0C 1b0 Latch high link fail inhibit indication 1b0 = Link fail inhibit assertion was never reported 1b1 = Link fail inhibit assertion was reported 3 send_s_sigdet_lh R/W0C 1b0 Latch high send_s_sigdet 1b0 = Send s sigdet assertion was never reported 1b1 = Send s sigdet assertion was reported 2 hi_rfer_lh R/W0C 1b0 Latch high hi rfer 1b0 = High ri rfer assertion was never reported 1b1 = High ri rfer assertion was reported 1 block_lock_ll R/W0S 1b0 Latch low block lock 1b0 = Block lock de-assertion was never reported 1b1 = Block lock de-assertion was never reported 0 pma_watchdog_ll R/W0S 1b0 Latch low pma watchdog status 1b0 = Low pma watchdof was reported 1b1 = Low pma watchdog was never reported www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 101 |
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