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PDP83TG720SWCSTQ1 Datasheet(PDF) 103 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 103 Page - Texas Instruments |
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103 / 199 page ![]() 7.6.2.47 LINK_QUAL_4 Register (Address = 0x548) [reset = 0x0] LINK_QUAL_4 is shown in Table 7-70. Return to the Summary Table. Table 7-70. LINK_QUAL_4 Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 15b0000000 00000000 Reserved 0 comm_ready R 1b0 Communication ready status (TC12) www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 103 |
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