PDP83TG720SWCSTQ1 datasheet(105/199 Pages) TI

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7.6.2.49 DATA_SCR_CFG Register (Address = 0x55A) [reset = 0x0]

DATA_SCR_CFG is shown in Table 7-72.

Return to the Summary Table.

Table 7-72. DATA_SCR_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

1b0

Reserved

14-6

cfg_ecc_error

R/W

9b00000000

9 bit error val xor'ed to memory data input for ECC testing

cfg_ecc_corrupt

R/W

1b0

Enable corruption of memory data for ECC testing

cfg_rx_delay_data_scr

R/W

1b0

Delay generation of rx descrmabler symbols by 1 bit

1b0 = Do not delay generation of rx descrmabler symbols by 1 bit

1b1 = Delay generation of rx descrmabler symbols by 1 bit

cfg_tx_delay_data_scr

R/W

1b0

Delay generation of tx scrmabler symbols by 1 bit

1b0 = Do not delay generation of tx scrmabler symbols by 1 bit

1b1 = Delay generation of tx scrmabler symbols by 1 bit

cfg_rx_data_scr_order_inv R/W

1b0

Enable to generate rx descrambler symbols from S[0] instead of

S[14] Valid only if LP's 0x55A[1] is set (TI-TI link)

1b0 = Use S[14] as rx descrambler symbols

1b1 = Use S[0] as rx descrmabler symbols

cfg_tx_data_scr_order_inv R/W

1b0

Enable to generate tx scrambler symbols from S[0] instead of S[14]

Valid only if LP's 0x55A[2] is set (TI-TI link)

1b0 = Use S[14] as tx scrambler symbols

1b1 = Use S[0] as tx scrmabler symbols

cfg_data_scr_bypass

R/W

1b0

Bypass data scrmabler on Tx as well as Rx path

1b0 = Do not bypass data scramblers

1b1 = Bypass data scramblers

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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PDP83TG720SWCSTQ1 Datasheet(PDF) 105 Page - Texas Instruments

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