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PDP83TG720SWCSTQ1 Datasheet(PDF) 108 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 108 Page - Texas Instruments |
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108 / 199 page ![]() 7.6.2.52 TEST_MEM_CFG Register (Address = 0x561) [reset = 0x17A0] TEST_MEM_CFG is shown in Table 7-75. Return to the Summary Table. Table 7-75. TEST_MEM_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 3b000 Reserved 12-6 cfg_wait_time_xcorr_wen R/W 7b1011110 Wait timer after TX_SEND_S after which testmem is written on energy fall Note : Valid only if 0x561[3] is set 5 cfg_xcorr_dbg_sel R/W 1b1 0b = Select xcorr from aligned detector to write to test mem 1b = Select xcorr from shifted detector to write to test mem Note : Valid only if 0x561[3] is set 4 cfg_send_s_infinite_loop R/W 1b0 enable transmitting infinite send_s sequence. For send_s debug. Valid only in master and when 0x56A[15] is set. 1b0 = disable infinte send_s mode 1b1 = enable infinite send_s mode 3 cfg_xcorr_dbg_test_mem R/W 1b0 enabled xcorr debug for send_s. Valid only if 0x561[0] is 1'b0 1b0 = Normal send_s debug. Refer to 0x561[1] 1b1 = Enabled xcorr debug 2 cfg_ecc_en R/W 1b0 Enable ECC logic for RS decoder memory 1b0 = ECC encoding/decoding is disabled 1b1 = ECC encoding/decoding is enabled 1 cfg_test_mem_sigdet_deb ug R/W 1b0 Enable sidget debug mode in test mem send s mode Valid only if 0x561[0] is 1'b0 1b0 = Test mem written in send s mode only on state transition 1b1 = Enable sigdet debug mode in test mem send s mode 0 cfg_pcs_test_mem_mode R/W 1b0 Choose send s or train rx test mem mode 1b0 = Send s info on test mem 1b1 = Train rx info on test mem DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 108 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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