PDP83TG720SWCSTQ1 datasheet(111/199 Pages) TI

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7.6.2.55 RGMII_CTRL Register (Address = 0x600) [reset = 0x120]

RGMII_CTRL is shown in Table 7-78.

Return to the Summary Table.

Table 7-78. RGMII_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

RESERVED

6b000000

Reserved

9-7

rgmii_rx_half_full_th

R/W

3b010

RGMII RX sync FIFO half full threshold

6-4

rgmii_tx_half_full_th

R/W

3b010

RGMII TX sync FIFO half full threshold

rgmii_tx_if_en

R/W

1b0

RGMII enable bit Default from strap

1b0 = RGMII disable

1b1 = RGMII enable

invert_rgmii_txd

R/W

1b0

Invert RGMII Tx wire order - full swap [3:0] to [0:3]

1b0 = Keep RGMII Tx wire order same - [3:

1b1 = Invert RGMII Tx wire order - [3:

invert_rgmii_rxd

R/W

1b0

Invert RGMII Rx wire order - full swap [3:0] to [0:3]

1b0 = Keep RGMII Rx wire order same - [3:

1b1 = Invert RGMII Rx wire order - [3:

sup_tx_err_fd

R/W

1b0

1: suppress tx_err in full duplex mode when tx_en set to zero 0:

allow tx_err assertion to PHY when tx_en set to zero (this bit can

disable the TX_ERR indication input)

1b0 = allow tx_err assertion to PHY when tx_en set to zero

1b1 = suppress tx_err in full duplex mode when tx_en set to zero

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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