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PDP83TG720SWCSTQ1 Datasheet(PDF) 113 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 113 Page - Texas Instruments |
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113 / 199 page  7.6.2.57 RGMII_DELAY_CTRL Register (Address = 0x602) [reset = 0x0] RGMII_DELAY_CTRL is shown in Table 7-80. Return to the Summary Table. Table 7-80. RGMII_DELAY_CTRL Register Field Descriptions Bit Field Type Reset Description 15-2 RESERVED R 14b0000000 0000000 Reserved 1 rx_clk_sel R/W 1b0 In RGMII mode, Enable or disable the internal delay for RXD wrt RX_CLK (use this mode when RGMII_RX_CLK and RGMII_RXD are aligned). The delay magnitude can be configured by programming register 0x430[7:4] 1b0 = clock and data are aligned 1b1 = clock on PIN is delayed by 90 degrees relative to RGMII_RX data 0 tx_clk_sel R/W 1b0 In RGMII mode, Enable or disable the internal delay for TXD wrt TX_CLK (use this mode when RGMII_TX_CLK and RGMII_TXD are aligned). The delay magnitude can be configured by programming register 0x430[11:8] 1b0 = clock and data are aligned 1b1 = clock is internally delayed by 90 degrees www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 113 |
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