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PDP83TG720SWCSTQ1 Datasheet(PDF) 182 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 182 Page - Texas Instruments |
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182 / 199 page ![]() 7.6.2.124 AN_CFG Register (Address = 0x7200) [reset = 0x0] AN_CFG is shown in Table 7-147. Return to the Summary Table. Table 7-147. AN_CFG Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 15b0000000 00000000 Reserved 0 mr_main_reset R/WSC 1b0 1 = Reset link sync/autoneg Note - RW bit Note - Added 7 to [15:12] to differentiate DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 182 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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