SH79F6488PSLASH080PR datasheet(127/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

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8.12 Power Management

8.12.1 Features

 Two power saving modes: Idle mode and Power-Down mode

 Two ways to exit Idle and Power-Down mode: interrupt and reset

To reduce power consumption, SH79F6488/SH79F6489 supplies two power saving modes: Idle mode and Power-Down mode.

These two modes are controlled by PCON & SUSLO register.

8.12.2 Idle Mode

In this mode, the clock to CPU is frozen, the program execution is halted, and the CPU will stop at a defined state. But the

peripherals continue to be clocked. When entering idle mode, all the CPU status before entering will be preserved. Such as:

PSW, PC, SFR & RAM are all retained.

By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the IDL bit in PCON

the CPU will clear either SUSLO register or IDL bit in the next machine cycle. And the CPU will not enter Idle mode. The setting

of IDL bit will be the last instruction that CPU executed.

There are two ways to exit Idle mode:

(1) An interrupt generated. The clock to the CPU will be restored, and the hardware will clear SUSLO register and IDL bit in

PCON register. Then the program will execute the interrupt service routine first, and then jumps to the instruction

immediately following the instruction that activated Idle mode.

(2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the

CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F6488/SH79F6489

will be reset. And the program will execute from address 0000H. The RAM will keep unchanged and the SFR value might be

changed according to different function module.

8.12.3 Power-Down Mode

The Power-Down mode places the SH79F6488/SH79F6489 in a very low power state. Power-Down mode will stop all the

clocks including CPU and peripherals. If WDT is enabled, WDT block will keep on working. When entering Power-Down mode,

all the CPU status before entering will be preserved. Such as: PSW, PC, SFR & RAM are all retained.

By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the PD bit in PCON register,

will make SH79F6488/SH79F6489 enter Power-Down mode. If the consecutive instruction sequence requirement is not met, the

CPU will clear either SUSLO register or PD bit in the next machine cycle. And the CPU will not enter Power-Down mode.

The setting of PD bit will be the last instruction that CPU executed.

Note: If IDL bit and PD bit are set simultaneously, the SH79F6488/SH79F6489 enters Power-Down mode. The CPU will not go in

Idle mode when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode.

There are four ways to exit the Power-Down mode:

(1) An active external Interrupt such as INT0, INT1 ,INT2 ,INT3 & INT4 will make SH79F6488/SH79F6489 exit Power-Down

mode. The oscillator will start after interrupt happens, after warm-up time, the clocks to the CPU and peripheral will be

restored, the SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes with the

interrupt service routine. After completion of the interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Power-Down mode.

(2) Timer3 interrupt will make SH79F6488/SH79F6489 exit Power-Down mode when 32.768kHz is the clock source. The

oscillator will start after interrupt happens, after warm-up time, the clocks to the CPU and peripheral will be restored, the

SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes with the interrupt

service routine. After completion of the interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Power-Down mode.

(3) Base Timer interrupt will make SH79F6488/SH79F6489 exit Power-Down mode when 32.768kHz or 12MHz internal RC is

the clock source. The oscillator will start after interrupt happens, after warm-up time, the clocks to the CPU and peripheral

will be restored, the SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes

with the interrupt service routine. After completion of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Power-Down mode.

(4) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled). This will restore the clock to the

CPU after warm-up time, the SUSLO register and the PD bit in PCON register will be cleared by hardware, finally the

SH79F6488/SH79F6489 will be reset. And the program will execute from address 0000H. The RAM will keep unchanged

and the SFR value might be changed according to different function module.

Note:

(1) In order to entering Idle/Power-Down, it is necessary to add 3 NOPs after setting IDL/PD bit in PCON.

(2) In order to entering Idle/Power-Down,all ports are not floating,set to output or input with pull-high.

(3) In order to entering Idle/Power-Down,reserved pin of LQFP 64 package must be set to output or input with pull-high.

(4) After base timer or LCD on, if WDT is on ,WDT cannot be turn off in Power-Down mode.Therefore, users need to read or

write RSTSTAT register in case to WDT overflow.

SH79F6488P/080PR Datasheet(PDF) 127 Page - SINOWEALTH Electronic Ltd

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