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LSM6DSV320X Datasheet(PDF) 59 Page - STMicroelectronics |
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LSM6DSV320X Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 212 page  9.2 PIN_CTRL (02h) SDO, OCS_aux, SDO_aux pins pull-up register (R/W). This register is not reset during the software reset procedure (see bit 0 of the CTRL3 (12h) register). Table 29. PIN_CTRL register OIS_ PU_DIS SDO_ PU_EN IBHR_ POR_EN 0(1) 0(1) 0(1) IO_PAD_ STRENGTH_1 IO_PAD_ STRENGTH_0 1. This bit must be set to 0 for the correct operation of the device. Table 30. PIN_CTRL register description OIS_PU_DIS Disables pull-up on both OCS_aux and SDO_aux pins (for mode 1 and mode 2). For further details about the configuration of the pull-up resistors in mode 3, refer to Table 25. Default value: 0 (0: OCS_aux and SDO_aux pins with pull-up; 1: OCS_aux and SDO_aux pins pull-up disconnected) SDO_PU_EN Enables pull-up on SDO pin. For details, refer to Table 25. Default value: 0 (0: SDO pin pull-up disconnected; 1: SDO pin with pull-up) IBHR_POR_EN Selects the action that the device performs after "reset whole chip" I3C pattern. Default value: 1 (0: configuration reset (software reset + dynamic address reset); (1: global reset (POR reset)) IO_PAD_STRENGTH[1:0] Defines the drive strength for the interrupt pads. Default value: 11 (00: lowest strength (recommended for VDDIO ≥ 3.0 V); 01: intermediate strength (recommended for VDDIO ≥ 2.0 V and VDDIO < 3 V); 10: reserved (do not use); 11: highest strength (recommended for VDDIO < 2 V)) LSM6DSV320X Register description DS14623 - Rev 1 page 59/212 |
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