LSM6DSV320X datasheet(93/212 Pages) STMICROELECTRONICS

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9.52

CTRL2_XL_HG (4Dh)

Control register 2 high-g accelerometer (R/W)

Table 145. CTRL2_XL_HG register

0(1)

HG_USR_

OFF_ON_WU

0(1)

XL_HG_ST1

XL_HG_ST0

1. This bit must be set to 0 for the correct operation of the device.

Table 146. CTRL2_XL_HG register description

HG_USR_OFF_ON_WU

Drives the data with user offset correction to the high-g wake-up and high-g shock

XL_HG_ST[1:0]

High-g accelerometer self-test selection

(00: normal mode (default);

01: positive sign self-test;

10: negative sign self-test;

11: reserved)

9.53

CTRL1_XL_HG (4Eh)

Control register 1 high-g accelerometer (R/W)

Table 147. CTRL1_XL_HG register

XL_HG_

REGOUT_EN

HG_USR_

OFF_ON_OUT

ODR_XL_

HG_2

ODR_XL_

HG_1

ODR_XL_

HG_0

FS_XL_

HG_2

FS_XL_

HG_1

FS_XL_

HG_0

Table 148. CTRL1_XL_HG register description

XL_HG_REGOUT_EN

Enables read of high-g accelerometer channel from output registers UI_OUTX_L_A_OIS_HG

(34h) and UI_OUTX_H_A_OIS_HG (35h) through UI_OUTZ_L_A_OIS_HG (38h) and

UI_OUTZ_H_A_OIS_HG (39h)

HG_USR_OFF_ON_OUT Enables high-g accelerometer user offset functionality on output registers

ODR_XL_HG_[2:0]

High-g accelerometer ODR selection, see Table 149

FS_XL_HG_[2:0]

High-g accelerometer full-scale selection, see Table 150

Table 149. High-g accelerometer ODR selection

Code

ODR

Code

ODR

000

Power-down (default)

100

960 Hz

001

N/A

101

1.92 kHz

010

N/A

110

3.84 kHz

011

480 Hz

111

7.68 kHz

Table 150. High-g accelerometer full-scale selection

FS_XL_HG_[2:0]

Full scale [g]

000

±32

001

±64

010

±128

011

±256

100

±320

LSM6DSV320X

DS14623 - Rev 1

page 93/212

LSM6DSV320X Datasheet(PDF) 93 Page - STMicroelectronics

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