LSM6DSV320X datasheet(23/212 Pages) STMICROELECTRONICS

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5.1.2

I²C operation

The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low

transition on the data line while the SCL line is held high. After this has been transmitted by the controller, the bus

is considered busy. The next byte of data transmitted after the start condition contains the address of the target in

the first 7 bits and the eighth bit tells whether the controller is receiving data from the target or transmitting data to

the target. When an address is sent, each device in the system compares the first seven bits after a start

condition with its address. If they match, the device considers itself addressed by the controller.

The target address (TAD) associated to the LSM6DSV320X is 110101xb. The SDO/TA0 pin can be used to

modify the less significant bit of the device address. If the SDO/TA0 pin is connected to the supply voltage, LSb is

1 (address 1101011b); else if the SDO/TA0 pin is connected to ground, the LSb value is 0 (address 1101010b).

This solution permits to connect and address two different inertial modules to the same I²C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the

acknowledge clock pulse. A receiver that has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the LSM6DSV320X behaves like a target device and the following protocol must be

adhered to. After the start condition (ST) a target address is sent, once a target acknowledge (TAK) has been

returned, an 8-bit subaddress (SUB) is transmitted. The increment of the address is configured by the CTRL3

(12h) (IF_INC).

The target address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be

issued after the two subaddress bytes; if the bit is 0 (write) the controller transmits to the target with direction

unchanged. Table 12 explains how the TAD+read/write bit pattern is composed, listing all the possible

configurations.

Table 12. TAD+read/write patterns

Command

TAD[6:1]

TAD[0] = TA0

R/W

TAD+R/W

Read

110101

11010101 (D5h)

Write

110101

11010100 (D4h)

Read

110101

11010111 (D7h)

Write

110101

11010110 (D6h)

Table 13. Transfer when controller is writing one byte to target

Controller

SAD + W

SUB

DATA

Target

TAK

Table 14. Transfer when controller is writing multiple bytes to target

Controller

TAD + W

SUB

DATA

Target

TAK

Table 15. Transfer when controller is receiving (reading) one byte of data from target

Controller

TAD + W

SUB

TAD + R

NCAK

Target

TAK

DATA

Table 16. Transfer when controller is receiving (reading) multiple bytes of data from target

Controller

SAD+

SUB

SAD+R

MAK

NMAK

Target

TAK

DATA

LSM6DSV320X

Digital interfaces

DS14623 - Rev 1

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