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LSM6DSV320X Datasheet(PDF) 69 Page - STMicroelectronics |
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LSM6DSV320X Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 212 page  9.16 CTRL3 (12h) Control register 3 (R/W) Table 58. CTRL3 register BOOT BDU 0(1) 0(1) 0(1) IF_INC 0(1) SW_RESET 1. This bit must be set to 0 for the correct operation of the device. Table 59. CTRL3 register description BOOT Reboots memory content. This bit is automatically cleared. Default value: 0 (0: normal mode; 1: reboot memory content) BDU Block data update. Default value: 1 (0: continuous update; 1: output registers are not updated until LSB and MSB have been read) IF_INC Register address automatically incremented during a multiple byte access with a serial interface (I²C, MIPI I3C, or SPI). Default value: 1 (0: disabled; 1: enabled) SW_RESET Software reset, resets all control registers to their default value. This bit is automatically cleared. Default value: 0 (0: normal mode; 1: reset device) LSM6DSV320X Register description DS14623 - Rev 1 page 69/212 |
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