AS4SD4M16DG-10SLASHIT datasheet(7/50 Pages) AUSTIN

7 / 50 page

SDRAM

AS4SD4M16

Rev. 2.1 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

Type = Sequential

Type = Interleaved

0 - 1

1-0

0,1,2,3

1,2,3,0

1,0,3,2

2,3,0,1

3,0,1,2

3,2,1,0

0,1,2,3,4,5,6,7

1,2,3,4,5,6,7,0

1,0,3,2,5,4,7,6

2,3,4,5,6,7,0,1

2,3,0,1,6,7,4,5

3,4,5,6,7,0,1,2

3,2,1,0,7,6,5,4

4,5,6,7,0,1,2,3

5,6,7,0,1,2,3,4

5,4,7,6,1,0,3,2

6,7,0,1,2,3,4,5,

6,7,4,5,2,3,0,1

7,0,1,2,3,4,5,6

7,6,5,4,3,2,1,0

Cn, Cn+1, Cn+2,

Cn+3, Cn+4…

Not Supported

…Cn-1,

Cn…

BURST DEFINITION

Table 1

Full Page

(y)

n = A0 - A9

location 0 - y

Order of Access Within a Burst

Burst

Length

Starting Column

Address

A11

A10

Address Bus

M3=0

M3=1

000

001

010

011

Reserved

Full Page

Reserved

000

001

010

011

100

101

110

111

Reserved

Burst Type

Sequential

* Should program M11,

M10=0,0 to ensure

compatibility with future

devices.

CAS Latency

Single Location Access

M6 - M0

Defined

Operating Mode

Standard Operation

All other states reserved

Write Burst Mode

Programmed Burst Length

Interleave

Mode Register(Mx)

Burst Length

Reserved*

Op Mode

CAS Latency

Burst Length

BURST TYPE

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting column

address, as shown in Table 1.

NOTE:

For full-page accesses: y = 256 (x16).

For a burst length of two, A1-A7 (x16)

select the block-of-two burst; A0 selects

the starting column within the block.

For a burst length of four, A2-A7 (x16)

select the block-of-four burst; A0-A1

select the starting column within the

block.

For a burst length of eight, A3-A7 (x16)

select the clock-of-eight burst; A0-A2

select the starting column within the

block.

For a full-page burst, the full row is

selected and A0-A7 (x16) select the

starting column.

Whenever a boundary of the block is

reached within a given sequence above,

the following access wraps within the

block.

For a burst length of one, A0-A7 (x16)

select the unique column to be accessed,

and Mode Register bit M3 is ignored.

FIGURE 1

MODE REGISTER DEFINITION

AS4SD4M16DG-10/IT Datasheet(PDF) 7 Page - Austin Semiconductor

AS4SD4M16DG-10/IT Datasheet(HTML) 7 Page - Austin Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL