AS4SD4M16DG-10SLASHIT datasheet(9/50 Pages) AUSTIN

9 / 50 page

SDRAM

AS4SD4M16

Rev. 2.1 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

TRUTH TABLE 1- Commands and DMQ Operation

(Note: 1)

NAME (FUNCTION)

CS\

RAS\

CAS\

WE\ DQM

ADDR

DQs

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (select bank and activate row)

Bank/Row

READ (select bank and column and start READ burst)

Bank/Col

WRITE (select bank and column and start WRITE burst)

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (deactivate row in bank or banks)

Code

LOAD MODE REGISTER

OpCode

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

X6,7

AUTO REFRESH or SELF REFRESH (enter self refresh

mode)

COMMANDS

Truth Table 1 provides a quick reference of available commands.

This is followed by a written description of each command.

Two additional Truth Tables appear following the Operation

section; these tables provide current state/next state informa-

tion.

NOTE:

CKE is HIGH for all commands shown except SELF REFRESH.

A0-A11 define the op-code written to the Mode Register.

A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10

LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are

“Don’t Care.”

This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

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