AS4SD4M16DG-10SLASHIT datasheet(33/50 Pages) AUSTIN

33 / 50 page

SDRAM

AS4SD4M16

Rev. 2.1 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

NOTES

All voltages referenced to V

This parameter is sampled. V

, V

Q = +3.3V; f = 1

MHz, T

= 25°C; pin under test biased at 1.4V.

is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle time

and the outputs open.

Enables on-chip refresh and address counters.

The minimum specifications are used only to indicate

cycle time at which proper operation over the full

temperature range (-55°C

≤ T

A ≤

+125°C) is ensured.

An initial pause of 100

µs is required after power-up,

followed by two AUTO REFRESH commands, before

proper device operation is ensured. (V

and V

Q must

be powered up simultaneously. V

and V

Q must be at

same potential.) The two AUTO REFRESH command

wake-ups should be repeated any time the t

REF

refresh

requirement is exceeded.

AC characteristics assume t

= 1ns.

In addition to meeting the transition rate specification,

the clock and CKE must transit between V

and V

(or

between V

and V

) in a monotonic manner.

Outputs measured at 1.5V with equivalent load:

10. t

defines the time at which the output achieves the

open circuit condition; it is not a reference to V

. The last valid data element will meet t

before

going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V, with

timing referenced to 1.5V crossover point.

12. Other input signals are allowed to transition no more

than once in any 30ns period (20ns on -8) and are

otherwise at valid V

or V

levels.

13. I

specifications are tested after the device is properly

initialized.

14. Timing actually specified by t

CKS

; clock(s) specified as a

reference only at minimum cycle rate.

15. Timing actually specified by t

plus t

; clock(s)

specified as a reference only at minimum cycle rate.

16. Timing actually specified by t

17. Required clocks are specified by JEDEC functionality

and are not dependent on any timing parameter.

18. The I

current will decrease as the CAS latency is

reduced. This is due to the fact that the maximum cycle

rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every 30ns

(20ns on -8).

20. CLK must be toggled a minimum of two times during this

period.

21. Based on t

= 100 MHz for -8 and 66 MHz for -10.

22. These five parameters vary between speed grades and

define the differences between the -8 SDRAM speeds:

-8.

23. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

≤ 10ns, and the pulse width cannot be greater than

one third of the cycle rate. V

undershoot: V

(MIN) =

-2V for a pulse width

≤ 10ns, and the pulse width cannot

be greater than one third of the cycle rate.

24. The clock frequency must remain constant during access

or precharge states (READ, WRITE, including t

, and

PRECHARGE commands). CKE may be used to reduce

the data rate.

25. Auto precharge mode only. The precharge timing budget

( t

) begins 8ns after the first clock delay, after the last

WRITE is executed.

26. Precharge mode only.

27. JEDEC and PC100 specify three clocks.

50pF

AS4SD4M16DG-10/IT Datasheet(PDF) 33 Page - Austin Semiconductor

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