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AS4SD4M16DG-10/IT Datasheet(PDF) 31 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 31 Page - Austin Semiconductor |
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31 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 31 Austin Semiconductor, Inc. SYMBOL MAX UNITS NOTES CI1 4.0 pF 2 CI2 5.0 pF 2 CIO 6.5 pF 2 PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs MIN MAX MIN MAX CL = 3 tAC 6.5 7 ns CL = 2 tAC 99 ns 22 Address hold time tAH 11 ns Address setup time tAS 23 ns CLK high-level width tCH 3 3.5 ns CLK low-level width tCL 3 3.5 ns CL = 3 tCK 810 ns 24 CL = 2 tCK 12 15 ns 22, 24 CKE hold time tCKH 11 ns CKE setup time tCKS 23 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 11 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 23 ns Data-in hold time tDH 11 ns Data-in setup time tDS 23 ns CL = 3 tHZ 68 ns 10 CL = 2 tHZ 710 ns 10 Data-out low-impedance time tLZ 11 ns Data-out hold time tOH 2.5 2.5 ns ACTIVE to PRECHARGE command tRAS 50 80,000 60 80,000 ns AUTO REFRESH, ACTIVE command period tRC 80 90 ns 22 ACTIVE to READ or WRITE delay tRCD 20 30 ns 22 Refresh period (4,096 rows) -40 to +85 degrees C tREF 64 64 ms Refresh period (4,096 rows) -55 to +125 degrees C tREF 16 16 ms PRECHARGE command period tRP 24 30 ns 22 ACTIVE bank A to ACTIVE bank B command tRRD 20 20 ns Transition time tT 0.3 1.2 1 1.2 ns 7 1 CLK + 1 CLK + - 25 8ns 8ns 15 15 ns 26 Exit SELF REFRESH to ACTIVE command tXSR 80 90 ns 20 Clock cycle time Data-out high-impedance time WRITE recovery time A2 version NOTES PARAMETER SYM Access time from CLK (pos. edge) -8 -10 UNITS tWR CAPACITANCE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 5, 6, 8, 9, 11) (-55oC<T A <+125oC) |
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