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AS4SD4M16DG-10/IT Datasheet(PDF) 34 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 34 Page - Austin Semiconductor |
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34 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 34 Austin Semiconductor, Inc. TIMING PARAMETERS * CAS latency indicated in parentheses. NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. 2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care”. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. MIN MAX MIN MAX tAH 11 ns tAS 23 ns tCH 3 3.5 ns tCL 3 3.5 ns tCK (3) 810 ns tCK (2) 12 15 ns tCKH 11 ns SYMBOL* UNITS -8 -10 MIN MAX MIN MAX tCKS 2 3 ns tCMH 1 1 ns tCMS 2 3 ns tMRD (3) 2 2 tCK tRC 80 90 ns tRP 24 30 ns SYMBOL* UNITS -8 -10 INITIALIZE AND LOAD MODE REGISTER2 12345 12345 12345 12345 12345 t CK tCH tCL T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3 12 12 12 12 12 12 12 12 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 123 123 12345 12345 12345 12345 1 1 1 1 tCKS tCKH 12 12 12 12 12 12 12 12 1234 1234 1234 1234 12 12 12 12 12 12 12 12 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 123 123 123 123 123 123 123 123 12 12 12 12 1234 1234 1234 1234 12 12 12 12 12 12 12 12 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 123 123 123 123 123 123 123 123 12 12 12 12 1234 1234 1234 1234 123 123 123 123 12 12 12 12 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 123 123 123 123 12 12 12 12 12 12 12 12 1234 1234 1234 1234 123 123 123 123 123 123 123 123 12345 12345 12345 12345 123 123 123 123 1 1 1 1 NOP tCMH tCMS 123 123 123 123 PRECHARGE 123 123 123 123 123 123 123 123 NOP NOP AUTO REFRESH 123 123 123 123 AUTO REFRESH 123 123 123 123 NOP NOP 123 123 123 123 LOAD MODE REGISTER 123 123 123 123 NOP 123 123 123 123 ACTIVE 123 123 123 123 tCMH tCMS tCMH tCMS 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 123456789012345678901234567890121234567890123456789012345678901212345678901234567890 12345 12345 12345 12345 12345678901234567890123456789012123456789012345678901 12345678901234567890123456789012123456789012345678901 12345678901234567890123456789012123456789012345678901 12345678901234567890123456789012123456789012345678901 12 12 12 12 CODE ROW 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1 1 1 1 1 1 1 1 12345 12345 12345 12345 1234 1234 1234 1234 12 12 12 12 12345 12345 12345 12345 12345 12345678901 12345678901 12345678901 12345678901 12345678901 12 12 12 12 12 ALL BANKS SINGLE BANK 12345 12345 12345 12345 12345 123456789012345678901234567890121 123456789012345678901234567890121 123456789012345678901234567890121 123456789012345678901234567890121 123456789012345678901234567890121 12 12 12 12 12 tAS tAH CODE tAS tAH 12 12 12 12 12 ROW 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1 1 1 1 1 1 1 1 1 1 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 12 12 12 12 12 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 12345678901 12345678901 12345678901 12345678901 12345678901 12 12 12 12 12345 12345 12345 12345 12345 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 12 12 12 12 1 1 1 1 ALL BANKS BANK 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 12 12 12 12 High-Z T=100s tRP tRC tMRD Power-up: V DD and CLK stable Precharge all banks AUTO REFRESH AUTO REFRESH tRC Program Mode Register 1,3,4 CLK CKE COMMAND DQM / DQML, DQMH A0-A9, A11 A10 BA0, BA1 DQ 12 12 12 12 12 12 12 12 1234 1234 1234 1234 12 12 12 12 12 12 12 12 1234 1234 1234 1234 1234 1234 1234 Don’t Care Undefined |
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