SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

AS4SD4M16

AS4SD4M16

Rev. 2.1 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

29

Austin Semiconductor, Inc.

NOTE (continued):

8.

CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted

by bank m’s burst.

9.

Burst in bank n continues as initiated.

10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank

m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE

command to prevent bus contention.

12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE

to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank

m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will

interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered

(Figure 24).

15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m

will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus

contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will

begin after t

WR

is met, where t

WR

begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in

registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m

will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t

WR

is met, where t

WR

begins when

the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m

(Figure 27).