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AS4SD4M16DG-10/IT Datasheet(PDF) 24 Page - Austin Semiconductor

Part # AS4SD4M16DG-10/IT
Description  4 Meg x 16 SDRAM Synchronous DRAM Memory
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Manufacturer  AUSTIN [Austin Semiconductor]
Direct Link  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

AS4SD4M16DG-10/IT Datasheet(HTML) 24 Page - Austin Semiconductor

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SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
AS4SD4M16
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
Austin Semiconductor, Inc.
WRITE with AUTO PRECHARGE
3.
Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-out
appearing CAS latency later. The PRECHARGE to bank
will begin after
t
WR
is met, where
t
WR
begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
4
Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE to
bank n will begin after
t
WR
is met, where
t
WR
begins when
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank 1 (Figure 27).
Figure 26
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ
NOTE: DQM is LOW.
D
IN a
D
IN
a+1
D
OUT d
D
OUT d+1
ADDRESS
DQ
123456
123456
123456
123456
1234567
1234567
1234567
1234567
1234
1234
1234
1234
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123
123
123
123
123456
123456
123456
123456
1234567
1234567
1234567
1234567
1234
1234
1234
1234
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123
123
123
123
1234567
1234567
1234567
1234567
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123
123
123
123
BANK
n,
COL
a
BANK
m,
COL
d
t
WR
- BANK
n
123456
123456
123456
123456
123456
123456
123456
123456
123
123
123
123
T0
T1
T2
T3
T4
T5
NOP
NOP
WRITE-AP
BANK
n
NOP
NOP
CLK
COMMAND
T6
NOP
T7
NOP
WRITE-AP
BANK
m
CAS Latency = 3 (BANK
m)
Page Active
WRITE with burst of 4
Interrupt Burst, Write back
Precharge
READ with burst of 4
Page Active
Internal
States
BANK n
BANK m
t
RP
-BANK
n
t
RP
-BANK
m
Figure 27
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
NOTE: DQM is LOW.
D
IN a
D
IN
a+1
ADDRESS
DQ
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123
123
123
123
1234567
1234567
1234567
1234567
123456
123456
123456
123456
123
123
123
123
123456
123456
123456
123456
1234567
1234567
1234567
1234567
1234
1234
1234
1234
1234567
1234567
1234567
1234567
1234567
1234567
1234567
1234567
123
123
123
123
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123456
123456
123456
123456
123
123
123
123
BANK
n,
COL
a
BANK
m,
COL
d
t
WR
- BANK
n
123456
123456
123456
123456
1234567
1234567
1234567
1234567
123
123
123
123
T0
T1
T2
T3
T4
T5
NOP
NOP
WRITE-AP
BANK
n
NOP
NOP
CLK
COMMAND
T6
NOP
T7
NOP
WRITE-AP
BANK
m
Page Active
WRITE with burst of 4
Interrupt Burst, Write back
Precharge
WRITE with burst of 4
Page Active
Internal
States
BANK n
BANK m
t
RP
-BANK
n
t
WR
-BANK
m
Write back
D
IN
a+2
D
IN
d
D
IN
d+1
D
IN
d+2
D
IN
d+3
123
123
123
123
Don’t Care



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