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AS4SD4M16DG-10/IT Datasheet(PDF) 37 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 37 Page - Austin Semiconductor |
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37 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 37 Austin Semiconductor, Inc. tCK tCL t CH T0 T1 T2 Tn +1 To +1 12 12 12 12 123 123 123 123 12 12 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 123 123 123 123 123 123 123 123 tCKS tCKH 123 123 123 123 12 12 12 12 1234 1234 1234 1234 123 123 123 123 12 12 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 123 123 123 12345 12345 12345 12345 12345 123 123 123 123 123 PRECHARGE NOP 12 12 12 12 123 123 123 123 123 ACTIVE 123 123 123 123 123 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 ROW 12345 12345 12345 12345 1234567890123456789012345678901212345678901234567890123456789012 1234567890123456789012345678901212345678901234567890123456789012 1234567890123456789012345678901212345678901234567890123456789012 1234567890123456789012345678901212345678901234567890123456789012 12 12 12 12 123456 123456 123456 123456 12345 12345 12345 12345 ALL BANKS SINGLE BANK 123456 123456 123456 123456 123456 123456 123456 123456 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 12 12 12 12 12 12 12 12 ROW 123456 123456 123456 123456 1234 1234 1234 1234 1 1 1 1 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 1234567890123456789012345678901212345678901234567890 12 12 12 12 12 12 12 12 BANK 123456 123456 123456 123456 12345 12345 12345 12345 1 1 1 1 BANK(S) tCMS tCMH AUTO REFRESH tAS tAH High-Z CLK CKE COMMAND DQM / DQML, DQMH A0-A9, A11 A10 BA0, BA1 DQ 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 123 123 123 123 123 123 123 123 12 12 12 12 1234 1234 1234 1234 123 123 123 123 12 12 12 12 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 123 123 123 123 12 12 12 12 123 123 123 123 1234 1234 1234 1234 12 12 12 12 12 12 12 12 123 123 123 123 123 NOP NOP 123 123 123 123 123 AUTO REFRESH 12 12 12 12 12 NOP NOP 1234 1234 1234 1234 12 12 12 12 tRP tRC tRC 123 123 123 12345 12345 12345 12345 Don’t Care Undefined AUTO REFRESH MODE1 TIMING PARAMETERS * CAS latency indicated in parentheses. MIN MAX MIN MAX tAH 1 1 ns tAS 2 3 ns tCH 3 3.5 ns tCL 3 3.5 ns tCK (3) 8 10 ns tCK (2) 12 15 ns SYMBOL* UNITS -10 -8 MIN MAX MIN MAX tCKH 11 ns tCKS 23 ns tCMH 11 ns tCMS 23 ns tRC 80 90 ns tRP 24 30 ns SYMBOL* UNITS -10 -8 NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. |
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