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AS4SD4M16DG-10/IT Datasheet(PDF) 40 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 40 Page - Austin Semiconductor |
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40 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 40 Austin Semiconductor, Inc. 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12 12 12 12 12 123 123 123 123 123 1234 1234 1234 1234 1234 12 12 12 12 12 12 12 12 12 12 t CK t CH t CL 123456 123456 123456 123456 123456 12 12 12 12 12 123 123 123 123 123 1234 1234 1234 1234 1234 12 12 12 12 12 123 123 123 123 123 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 1234 12 12 12 12 12 123 123 123 123 123 t CKS tCKH t CMS tCMH 123 123 123 123 123 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 123 123 123 123 123 123 123 123 123 123 123456 123456 123456 123456 123456 ACTIVE NOP READ NOP NOP NOP NOP 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 1234567890123456789 12345678 12345678 12345678 12345678 12345678 12345678 12345678 123456 123456 123456 123456 123456 CMH 12 12 12 12 12 123 123 123 123 123 1234 1234 1234 1234 1234 12 12 12 12 12 12 12 12 12 12 123 123 123 123 123 123456789012345678901234567890 123456789012345678901234567890 123456789012345678901234567890 123456789012345678901234567890 123456789012345678901234567890 123 123 123 123 123 123 123 123 123 123 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 12345678 12345678 12345678 ROW 1234567 1234567 1234567 1234567 1234567 12345 12345 12345 12345 t CMS t AH t AS t ROW AH t AS t 123 123 123 123 123 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 12345678 12345678 12345678 BANK 1234567 1234567 1234567 1234567 1234567 AH t AS t BANK 12 12 12 12 12 12 12 12 12 12 12345 12345 12345 12345 12345 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 12 12 12 12 12 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 12 12 12 12 12 123 123 123 123 123 1234 1234 1234 1234 1234 12 12 12 12 12 12 12 12 12 12 123 123 123 123 123 12 12 12 12 12 ACTIVE 123 123 123 123 123 12 12 12 12 12 12 12 12 12 12 12345 12345 12345 12345 12345 123 123 123 123 123 123 123 123 123 123 COLUMN m2 1 1 1 1 1 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678901234567890123456789012 12345678901234567890123456789012 12345678901234567890123456789012 12345678901234567890123456789012 123 123 123 123 123 123456 123456 123456 123456 123456 ROW 12345678 12345678 12345678 12345678 12345678 12 12 12 12 12 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 ROW ENABLE AUTO PRECHARGE 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567 1234567 1234567 1234567 1234567 12345 12345 12345 12345 12345 BANK READ -- WITH AUTO PRECHARGE1 123 123 123 123 123 123 123 123 123 123 1234 1234 1234 1234 1234 123 123 123 123 123 12 12 12 12 12 123456 123456 123456 123456 123456 1 1 1 1 1 12345678901234567890123456789012123456 12345678901234567890123456789012123456 12345678901234567890123456789012123456 12345678901234567890123456789012123456 12345678901234567890123456789012123456 12 12 12 12 12 12 12 12 12 12 T0 T1 T2 T3 T4 T5 T6 T7 T8 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 12 12 12 12 12 12 12 12 12 12 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 NOP 12345678 12345678 12345678 12345678 12345678 12345678 1234 1234 1234 1234 1234 1234 D OUT m t AC t LZ AC 123 123 123 123 123 123 D OUT m+1 1234 1234 1234 1234 1234 1234 tOH D OUT m+2 D OUT m+3 12 12 12 12 12 12 12 12 t RP t RC t RAS t RCD CAS Latency AC tOH AC tOH tOH tHZ t CLK CKE COMMAND DQM / DQML, DQMH A0-A9, A11 BA0, BA1 DQ A10 123 123 123 123 12345 12345 12345 12345 Don’t Care Undefined TIMING PARAMETERS NOTE: 1. For this example, the burst length = 4, the CAS latency = 2. 2. x16: A8, A9 and A11 = “Don’t Care.” * CAS latency indicated in parentheseses. MIN MAX MIN MAX tAC(3) 6.5 7 ns tAC(2) 99 ns tAH 11 ns tAS 23 ns tCH 33.5 ns tCL 33.5 ns tCK(3) 810 ns tCK(2) 12 15 ns tCKH 11 ns tCKS 23 ns UNITS SYMBOL* -8 -10 MIN MAX MIN MAX tAC(3) 6.5 7 ns tAC(2) 99 ns tAH 11 ns tAS 23 ns tCH 33.5 ns tCL 33.5 ns tCK(3) 810 ns tCK(2) 12 15 ns tCKH 11 ns tCKS 23 ns UNITS SYMBOL* -8 -10 MIN MAX MIN MAX tCMH 11 ns tCMS 23 ns tHZ(3) 68 ns tHZ(2) 710 ns tLZ 11 ns tOH 2.5 2.5 ns tRAS 50 80,000 60 80,000 ns tRC 80 90 ns tRCD 20 30 ns tRP 24 30 ns UNITS SYMBOL* -8 -10 |
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