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AS4SD4M16DG-10/IT Datasheet(PDF) 22 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 22 Page - Austin Semiconductor |
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22 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 Austin Semiconductor, Inc. CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regard- less of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9=0). NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. Figure 23 CLOCK SUSPEND DURING READ BURST 123 123 DON’T CARE CLK COMMAND ADDRESS DQ CKE INTERNAL CLOCK T0 T1 T2 T3 T4 T5 T6 1234 1234 1234 1234 12345 12345 12345 12345 12 12 NOP READ NOP NOP NOP NOP 1234 1234 1234 1234 1234 1234 1234 1234 12345 12345 12345 12345 12 12 12 1234 1234 1234 1234 12345 12345 12345 12345 12 12 12 12 1234 1234 1234 1234 12345 12345 12345 12345 12 12 12 12 1234 1234 1234 1234 12345 12345 12345 12345 123 123 123 12345 12345 12345 12345 1234 1234 1234 1234 123 123 123 BANK, COL n 1234 1234 1234 1234 1234 1234 1234 1234 12 12 12 D OUT n D OUT n+2 D OUT n+3 D OUT n+1 CLK COMMAND ADDRESS DQ 12345 12345 12345 123456 123456 123456 1234 1234 1234 123456 123456 123456 123456 123456 123456 123 123 123 WRITE NOP NOP NOP 12345 12345 12345 12345 12345 12345 123 123 123 12345 12345 12345 123456 123456 123456 123 123 123 12345 12345 12345 12345 12345 12345 123 123 123 123456 123456 123456 123456 123456 123456 123 123 123 12345 12345 12345 12345 12345 12345 12 12 12 BANK, COL n 12345 12345 12345 12 12 12 T0 T1 T2 T3 T4 T5 12345 12345 12345 12345 12345 12345 123 123 123 12345 12345 12345 123456 123456 123456 123 123 123 12345 12345 12345 12345 12345 12345 123 123 123 DIN n DIN n+1 DIN n+2 NOTE: For this example, burst length = 4 or greater, and DQM is LOW. Figure 22 CLOCK SUSPEND DURING WRITE BURST CKE INTERNAL CLOCK 12345 12345 12345 |
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