 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AS4SD4M16DG-10/IT Datasheet(PDF) 8 Page - Austin Semiconductor |
|
|
|||||||||||||||||||||||||||||
AS4SD4M16DG-10/IT Datasheet(HTML) 8 Page - Austin Semiconductor |
|
|
8 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 Austin Semiconductor, Inc. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown op- eration or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0- M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS LATENCY = 2 CAS LATENCY = 3 -8 ≤ 83 ≤ 125 -10 ≤ 66 ≤ 100 SPEED ALLOWABLE OPERATING FREQUENCY (MHz) CAS LATENCY Table 2 Figure 2 CAS LATENCY CLK COMMAMD DQ 123 123 123 123 123 123 123 123 123 123 123 123 T3 T2 T1 T0 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 12 12 12 12 12 12 12 12 NOP READ D OUT NOP 123 123 123 123 123 123 123 123 12 12 12 12 t LZ t OH t AC CAS Latency = 2 T4 123 123 123 123 123 123 123 123 123 123 123 123 T3 T2 T1 T0 NOP NOP READ 12345 12345 12345 12345 12 12 12 12 123 123 123 123 NOP 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 1 1 1 1 1 12 12 12 12 12 D OUT t AC t LZ t OH CAS Latency = 3 CLK COMMAMD DQ 123 123 123 123 123 123 DON’T CARE UNDEFINED |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
