DAC39J84IAAVR datasheet(30/146 Pages) TI

30 / 146 page

DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

www.ti.com

Table 3. Relationship Between Lane Rate and SerDes PLL Output

Frequency (continued)

RATE

LINE RATE

PLL OUTPUT FREQUENCY

Quarter

x Gbps

1x GHz

Eigth

x Gbps

2x GHz

Table 4. SerDes PLL Modes Selection

MPY

EFFECT

00010000

00010100

00011000

00100000

00100001

8.25x

00101000

10x

00110000

12x

00110010

12.5x

00111100

15x

01000000

16x

01000010

16.5x

01010000

20x

01011000

22x

01100100

25x

Other codes

reserved

The wide range of multiply factors combined with the different rate modes means it will often be possible to

achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the

highest reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop

filter depending on the operating frequency of the VCO. To indicate the selection the user must set the rw_cfgpll

[9] (VRANGE) bit. If the PLL output frequency is below 2.17GHz, VRANGE should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock

by setting the appropriate loop bandwidth via rw_cfgpll [12:11] (LB) bits. The loop bandwidth is obtained by

dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output

frequency as shown in Table 5.

Table 5. SerDes PLL Loop Bandwidth Selection

BWSCALE vs PLL OUTPUT FREQUENCY

EFFECT

3.125 GHz

2.17 GHz

1.5625 GHz

Medium loop bandwidth

Ultra high loop bandwidth

Low loop bandwidth

High loop bandwidth

An approximate loop bandwidth of 8–30MHz is suitable and recommended for most systems where the reference

clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input cell, but of

low quality, an approximate loop bandwidth of less than 8MHz may offer better performance. For systems where

the reference clock is cleaned via an ultra low jitter LC-based cleaner PLL, a high loop bandwidth up to 60MHz is

more appropriate. Note that the use of ultra high loop bandwidth setting is not recommended for PLL multiply

factor of less than 8.

Submit Documentation Feedback

Product Folder Links: DAC39J84

DAC39J84IAAVR Datasheet(PDF) 30 Page - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL