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DAC39J84IAAVR Datasheet(PDF) 79 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 79 Page - Texas Instruments

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DAC39J84
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SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
7.5.1.27 config26 Register – Address: 0x1A, Default: 0x0020
Figure 108. config26 Register Format
15
14
13
12
11
10
9
8
reserved
reserved
vbgr_ sleep
7
6
5
4
3
2
1
0
biasopamp_
tsense_ sleep
pll_sleep
clkrecv_sleep
daca_sleep
dacb_sleep
dacc_sleep
dacd_sleep
sleep
Table 57. config26 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config26
0x1A
15:10
reserved
Reserved
000000
9
reserved
Reserved
0
8
vbgr_ sleep
Turns off the Bandgap over internal R bias current generator bias
0
7
biasopamp_
Turns off the bias OP amp when high.
0
sleep
6
tsense_ sleep
Turns off the temperature sensor when asserted.
0
5
pll_sleep
Puts the DAC PLL into sleep mode when asserted.
1
4
clkrecv_sleep
When asserted the clock input receiver gets put into sleep mode. This
0
also affects the SYSREF receiver as well.
3
daca_sleep
When asserted DACA is put into sleep mode
0
2
dacb_sleep
When asserted DACB is put into sleep mode
0
1
dacc_sleep
When asserted DACC is put into sleep mode
0
0
dacd_sleep
When asserted DACD is put into sleep mode
0
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