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DAC39J84IAAVR Datasheet(PDF) 17 Page - Texas Instruments |
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DAC39J84IAAVR Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 146 page ![]() DAC39J84 www.ti.com SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015 Timing Requirements (continued) Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1x interpolation, NCO off, QMC off, Inverse sinc off(2) 162 2x Interpolation, NCO off, QMC off, Inverse sinc off(2) 245 4x Interpolation, NCO off, QMC off, Inverse sinc off(2) 401 8x Interpolation, NCO off, QMC off, Inverse sinc off(2) 740 16x Interpolation, NCO off, QMC off, Inverse sinc off(2) 1423 NCO 48 DAC clock Digital Latency QMC 32 cycles Inverse Sinc 36 PA Protection (pap_dlylen_sel = "0") 68 Dithering 0 Complex Summation 0 Coarse Fractional Delay 51 Fine Fractional Delay 52 (2) Measured latency from JESD buffer release to DAC output, LMF=442. 6.9 Switching Characteristics Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT (1) DAC outputs are updated on the falling edge of tpd Output propagation delay DAC clock. Does not include Digital Latency (see 2 ns below). tr(IOUT) Output rise time 10% to 90% 50 ps tf(IOUT) Output fall time 90% to 10% 50 ps (1) Measured single ended into 50 Ω load. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DAC39J84 |
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