DAC39J84IAAVR datasheet(86/146 Pages) TI

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DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

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7.5.1.36 config35 Register – Address: 0x23, Default: 0xFFFF

Figure 117. config35 Register Format

sleep_cntl

Table 66. config35 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config35

0x23

15:0

sleep_cntl

This controls the routing of the SLEEP pin signal to different blocks.

0xFFFF

Assertion means that the SLEEP signal will be sent to the block. These

bits do not override the SIF bits, just the SLEEP signal from the pin.

When asserted,

bit15 through bit9 = Not used

bit8 = Allows the Band gap over R to sleep (BUG… in this PG it is

hooked to bit7)

bit7 = Allows the Bias OP Amp to sleep

bit6 = Allows the TEMP Sensor to sleep

bit5 = Allows the PLL to sleep

bit4 = Allows the CLK_RECV to sleep

bit3 = Allows DACD to sleep

bit2 = Allows DACC to sleep

bit1 = Allows DACB to sleep

bit0 = Allows DACA to sleep

7.5.1.37 config36 Register – Address: 0x24, Default: 0x0000

Figure 118. config36 Register Format

reserved

cdrvser_ sysref_mode

reserved

Table 67. config36 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config36

0x24

15:13

reserved

Reserved

000

12:7

reserved

Reserved

000000

6:4

cdrvser_

Determines how SYSREF is used to sync the clock dividers in the device.

000

sysref_mode

000 = Don’t use SYSREF pulse

001 = Use all SYSREF pulses

010 = Use only the next SYSREF pulse

011 = Skip one SYSREF pulse then use only the next one

100 = Skip one SYSREF pulse then use all pulses.

3:2

reserved

Reserved

1:0

reserved

Reserved

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