DAC39J84IAAVR datasheet(72/146 Pages) TI

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DAC39J84

SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

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7.5.1.8 config7 Register – Address: 0x07, Default: 0x0000

Figure 89. config7 Register Format

memin_ tempdata

reserved

memin_lane_ skew

Table 38. config7 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config7 No

0x7

15:8

memin_ tempdata

This is the output from the chip temperature sensor. NOTE: when reading

0x00

RESET

these bits the SIF interface must be extremely slow, 1MHz range.

Value

7:5

reserved

Reserved

000

4:0

memin_lane_ skew

Measure of the lane skew for link0 only. Updated when the RBD is

0000

released and measured in terms of JESD clock.

NOTE: these bits are READ_ONLY

7.5.1.9 config8 Register – Address: 0x08, Default: 0x0000

Figure 90. config8 Register Format

reserved

qmc_offseta

Table 39. config8 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config8

0x8

reserved

Reserved

AUTO

reserved

Reserved

SYNC

reserved

Reserved

12:0

qmc_offseta

The DAC A offset correction. The offset is measured in DAC LSBs.

0x0000

NOTE: Writing this register causes an auto-sync to be generated in

the QMC OFFSET block.

7.5.1.10 config9 Register – Address: 0x09, Default: 0x0000

Figure 91. config9 Register Format

reserved

qmc_offsetb

Table 40. config9 Register Field Descriptions

Addr

Default

Bit

Name

Function

Name

(Hex)

Value

config9

0x9

15:13

reserved

Reserved

000

12:0

qmc_offsetb

The DAC B offset correction. The offset is measured in DAC LSBs.

0x0000

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