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DAC39J84IAAVR Datasheet(PDF) 76 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 76 Page - Texas Instruments

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
www.ti.com
7.5.1.18 config17 Register – Address: 0x11, Default: 0x0000
Figure 99. config17 Register Format
15
14
13
12
11
10
9
8
reserved
reserved
reserved
reserved
qmc_phasecd
7
6
5
4
3
2
1
0
qmc_phasecd
Table 48. config17 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config17
0x11
15
reserved
Reserved
0
AUTO
14
reserved
Reserved
0
SYNC
13
reserved
Reserved
0
12
reserved
Reserved
0
11:0
qmc_phasecd
The QMC correction phase term for the DACAD path. The range is –0.5 to
0x000
0.49975. Programming “100000000000” = –0.5. Programming
“011111111111” = 0.49975.
7.5.1.19 config18 Register – Address: 0x12, Default: 0x0000
Figure 100. config18 Register Format
15
14
13
12
11
10
9
8
phaseoffsetab
7
6
5
4
3
2
1
0
phaseoffsetab
Table 49. config18 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config18
0x12
15:0
phaseoffsetab
Phase offset for NCO in DACAB path
0x0000
AUTO
SYNC
7.5.1.20 config19 Register – Address: 0x13, Default: 0x0000
Figure 101. config19 Register Format
15
14
13
12
11
10
9
8
phaseoffsetcd
7
6
5
4
3
2
1
0
phaseoffsetcd
Table 50. config19 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config19
0x13
15:0
phaseoffsetcd
Phase offset for NCO in DACAB path
0x0000
AUTO
SYNC
76
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Product Folder Links: DAC39J84



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