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DAC39J84IAAVR Datasheet(PDF) 59 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 59 Page - Texas Instruments

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IOUTP
4 : 1
50 :
RLOAD
100 :
100 :
IOUTN
AGND
IOUTP
1 : 1
IOUTN
50 :
RLOAD
100 :
50 :
50 :
AGND
DAC39J84
www.ti.com
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
7.3.29 DAC Transfer Function
The DAC39J84 can be easily configured to drive a doubly terminated 50
Ω cable using a properly selected RF
transformer. Figure 77 and Figure 78 show the 50
Ω doubly terminated transformer configuration with 1:1 and 4:1
impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded
to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5 Vpp for a 1:1
transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the
transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer
results in an output between –0.5 V and +0.5 V.
Figure 77. Driving a Doubly Terminated 50
Ω Cable Using a 1:1 Impedance Ratio Transformer
Figure 78. Driving a Doubly Terminated 50
Ω Cable Using a 4:1 Impedance Ratio Transformer
7.4 Device Functional Modes
7.4.1 Clocking Modes
The DAC39J84 has a single differential clock DACCLKN/P to clock the DAC cores and internal digital logic. The
DAC39J84 DACCLK can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).
In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC
clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can
be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance
requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.
7.4.1.1 PLL Bypass Mode
In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock
the DAC39J84 DAC cores. This mode gives the device best performance and is recommended for extremely
demanding applications.
Copyright © 2014–2015, Texas Instruments Incorporated
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