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DAC39J84IAAVR Datasheet(PDF) 83 Page - Texas Instruments

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Part # DAC39J84IAAVR
Description  DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface
PDF  146 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39J84IAAVR Datasheet(HTML) 83 Page - Texas Instruments

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DAC39J84
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SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
7.5.1.32 config31 Register – Address: 0x1F, Default: 0x1111
Figure 113. config31 Register Format
15
14
13
12
11
10
9
8
syncsel_ mixerab
syncsel_ mixercd
7
6
5
4
3
2
1
0
syncsel_ nco
reserved
sif_sync
reserved
Table 62. config31 Register Field Descriptions
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config31
0x1F
15:12
syncsel_ mixerab
Select the sync for the mixerAB block. A ‘1’ in the selected bit place allows
0x1
the selected sync to pass to the block.
bit0 = auto-sync from SIF register write
bit1 = sysref
bit2 = sync_out from JESD
bit3 = sif_sync
11:8
syncsel_ mixercd
Select the sync for the mixerCD block. A ‘1’ in the selected bit place allows
0x1
the selected sync to pass to the block.
bit0 = auto-sync from SIF register write
bit1 = sysref
bit2 = sync_out from JESD
bit3 = sif_sync
7:4
syncsel_ nco
Select the sync for the NCO accumulators. A ‘1’ in the selected bit place
0x4
allows the selected sync to pass to the block.
bit0 = ‘0’
bit1 = sysref
bit2 = sync_out from JESD
bit3 = sif_sync
3:2
reserved
Reserved
00
1
sif_sync
This is the SIF SYNC signal.
0
0
reserved
Reserved
0
Copyright © 2014–2015, Texas Instruments Incorporated
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