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DAC39J84IAAVR Datasheet(PDF) 65 Page - Texas Instruments |
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DAC39J84IAAVR Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 146 page  DAC39J84 www.ti.com SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015 Table 30. Register Map (continued) (MSB) (LSB) Name Address Default Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 15 Bit 0, config67 0x43 0x0000 reserved config68 0x44 0x0000 reserved config69 0x45 0x0000 reserved config70 0x46 0x0044 lid0(4:0) lid1(4:0) lid2(4:0) reserved config71 0x47 0x190A lid3(4:0) lid4(4:0) lid5(4:0) reserved config72 0x48 0x31C3 lid6(4:0) lid7(4:0) reserved subclassv(2:0) jesdv config73 0x49 0x0000 link_assign(15:0) jesd config74 0x4A 0x001E lane_ena(7:0) jesd_test _seq(1:0) dual init_state(3:0) _reset_n config75 0x4B 0x0000 reserved rbd_m1(4:0) f_m1(7:0) config76 0x4C 0x0000 reserved k_m1(4:0) reserved reserved reserved l_m1(4:0) config77 0x4D 0x0300 m_m1(7:0) reserved s_m1(4:0) config78 0x4E 0x0F0F reserved nprime_m1(4:0) reserved hd scr n_m1(4:0) jesd match match no_lane config79 0x4F 0x1CC1 match_data(7:0) reserved _commaalign _specific _ctrl _sync _ena config80 0x50 0x0000 adjcnt_link0(3:0) adjdir_link0 bid_link0(3:0) cf_link0(4:0) cs_link0(1:0) config81 0x51 0x00FF did_link0(7:0) sync_request_ena_link0(7:0) disable phadj config82 0x52 0x00FF reserved _err_repor error_ena_link0(7:0) _link0 t _link0 config83 0x53 0x0000 adjcnt_link1(3:0) adjdir_link1 bid_link1(3:0) cf_link1(4:0) cs_link1(1:0) config84 0x54 0x00FF did_link1(7:0) sync_request_ena_link1(7:0) disable _err phadj config85 0x55 0x00FF reserved error_ena_link1(7:0) _report _link1 _link1 config86 0x56 0x0000 reserved reserved reserved reserved reserved config87 0x57 0x00FF reserved reserved config88 0x58 0x00FF reserved reserved reserved reserved config89 0x59 0x0000 reserved reserved reserved reserved reserved config90 0x5A 0x00FF reserved reserved config91 0x5B 0x00FF reserved reserved reserved reserved err_cnt err_cnt config92 0x5C 0x1111 reserved reserved reserved reserved sysref_mode_link1(2:0) sysref_mode_link0(2:0) _clr_link1 _clr_link0 config93 0x5D 0x0000 reserved config94 0x5E 0x0000 res1(7:0) res2(7:0) config95 0x60 0x0123 reserved octetpath_sel(0)(2:0) reserved octetpath_sel(1)(2:0) reserved octetpath_sel(2)(2:0) reserved octetpath_sel(3)(2:0) config96 0x61 0x0456 reserved octetpath_sel(4)(2:0) reserved octetpath_sel(5)(2:0) reserved octetpath_sel(6)(2:0) reserved octetpath_sel(7)(2:0) config97 0x62 0x000F syncn_pol reserved syncncd_sel(3:0) syncnab_sel(3:0) syncn_sel(3:0) config98 0x63 0x0000 reserved reserved reserved reserved config98 0x64 0x0000 reserved reserved reserved reserved Reserved Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Links: DAC39J84 |
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