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DAC39J84IAAVR Datasheet(PDF) 49 Page - Texas Instruments |
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DAC39J84IAAVR Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 146 page  DAC39J84 www.ti.com SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015 Table 16. Example Coefficient Sets for the Small Fractional Delay (continued) InvGain DELAY C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 NUMERATOR [Tdac] 1 -11 57 -226 2228 457 -145 44 -9 1 447952 0.17 1 -11 57 -225 2202 458 -145 44 -9 1 452483 0.172 1 -11 57 -225 2175 459 -145 44 -9 1 457495 0.174 1 -11 57 -224 2150 459 -145 44 -9 1 462222 0.176 1 -11 57 -224 2125 460 -145 44 -9 1 467047 0.178 1 -11 57 -223 2100 461 -145 44 -9 1 471767 0.18 1 -11 57 -223 2076 462 -145 44 -9 1 476583 0.182 1 -11 57 -223 2053 463 -145 44 -9 1 481283 0.184 1 -11 57 -222 2030 464 -145 44 -9 1 485856 0.186 1 -11 57 -222 2008 465 -146 44 -9 1 490741 0.188 1 -11 56 -221 1986 466 -146 44 -9 1 495497 0.19 1 -11 56 -221 1964 467 -146 44 -9 1 500346 0.192 1 -11 56 -220 1943 468 -146 44 -9 1 504815 0.194 1 -11 56 -220 1923 469 -146 44 -9 1 509365 0.196 1 -11 56 -219 1903 470 -146 44 -9 1 513752 0.198 7.3.16.2 Coarse Fractional Delay FIR Filter The coefficients of FIR filters for large fractional delay can only be chosen from a predefined set of values. Each set of values produces a specific delay with a step of 1/8×Tdac. The value of coefficients as well as their resultant fractional delay is provided in Table 17. Table 17. Available Coefficient Sets for Large Fractional Delay FIR InvGain DELAY lfras_coefsel_x C0 C1 C2 C3 C4 C5 C6 C7 NUMERATOR [Tdac] 000 -1 9 -39 532 76 -24 7 -1 7503 0.1250 001 -1 8 -35 259 87 -25 7 -1 14028 0.2500 010 -1 7 -31 168 101 -26 7 -1 18725 0.3750 011 -1 7 -27 122 122 -27 7 -1 20764 0.5000 100 — — — — — — — — — — 101 -1 7 -26 101 168 -31 7 -1 18725 06250 110 -1 7 -25 87 259 -35 8 -1 14028 0.7500 111 -1 7 -24 76 532 -39 9 -1 7503 0.8750 7.3.17 Output Multiplexer The DAC39J84 includes an output multiplexer before the digital to analog converters that allows any signal channel A-D to be routed to any DAC A-D. See pathx_out_sel for details on how to configure the cross-bar switches. 7.3.18 Power Measurement And Power Amplifier Protection DAC39J84 provides an optional mechanism to protect the Power Amplifier (PA) in cases when the signal power shows some abnormality. For example, if the data clock is lost, the FIFO would automatically generate a single tone signal, which causes abnormally high average power and could be dangerous to the PA. In the PA protection mechanism, the signal power is monitored by maintaining an sliding window accumulation of last N samples. N is selectable to be 64 or 128 based on the setting of pap_dlylen_sel. The average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (N). The result is then compared against a threshold (pap_vth). If the threshold is violated, the delayed input signal is divided by a value chosen by pap_gain, to form a scaled down version of the input signal. Since PAP output derives from a delay-line, there is deterministic latency of at least N cycles from the block input to block output. The PA protection is enabled by setting the pap_ena bit to “1”. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: DAC39J84 |
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