DAC39J84IAAVR datasheet(33/146 Pages) TI

Part #	DAC39J84IAAVR

Description	DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface

PDF	146 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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DAC39J84

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SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015

7.3.6 JESD204B Frame Assembly

The JESD204B defines the following parameters:

•

L is the number of lanes per link

•

M is the number of converters per device

•

F is the number of octets per frame clock period

•

S is the number of samples per frame

•

HD is the High-Density bit which controls whether a sample may be divided over more lanes.

Table 9 and Table 10 list the available JESD204B formats for the DAC39J84. Table 11 lists the speed limits of

the DAC39J84. The ranges are limited by the Serdes PLL VCO frequency range, the Serdes PLL reference clock

range, the maximum Serdes line rate, and the maximum DAC sample frequency.

Table 9. JESD204B Frame Assembly Byte Representation (Quad-channel)

LMF = 841

LMF = 442

LMF = 244

LMF = 148

Lane 0

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

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DAC39J84IAAVR Datasheet(PDF) 33 Page - Texas Instruments