SPC574K72E5 datasheet(72/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

The following supplies are involved:



HV—High voltage external power supply for voltage regulator module. This must be

provided externally through VDD_HV_PMC/VDD_HV_IO_MAIN power pin.



BV—High voltage external power supply for internal ballast module. This must be

provided externally through VDD_HV_PMC/VDD_HV_IO_MAIN power pins.



LV—Low voltage internal power supply for core, PLL and Flash digital logic. This is

generated by the internal voltage regulator but provided externally to allow connection

to a stability capacitor. It is further split into three main domains to ensure noise

isolation between critical LV modules:

–

LV_COR—Low voltage supply for the core. It is also used to provide supply

LV_PLL through double bonding.

–

LV_FLA—Low voltage supply for code flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

–

LV_PLL—Low voltage supply for PLL0. It is shorted to LV_COR through double

bonding.

Table 36. Device Power Supply Integration

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

CREG

SR D Internal voltage regulator stability

external capacitance

—1.3

2(3)

—µF

RREG

SR D Stability capacitor equivalent serial

resistance

Total resistance including

board track

——



CDECREGn SR D Internal voltage regulator

decoupling external capacitance

VDD_LV/VSS pair

100

—

RDECREGn SR D Stability capacitor equivalent serial

resistance

——

—



CDECBV

SR D Relay capacitance for ballast

power-up

—3

4(4)

—µF

CDECHV

SR D Decoupling capacitance regulator

supply

VDD_HV_IO_MAIN/VSS pair

100

—

VMREG

CC P Main regulator output voltage

Before trimming

1.14

1.28

1.4(5)

After trimming

1.14

1.28

1.32

IDDMREG

SR P Main regulator current provided to

VDD_LV domain

—

350

IDDCLAMP CC D Main regulator rush current sinked

from VDD_HV_IO_MAIN domain

during VDD_LV external

capacitance loading

Power-up condition

200

—

1500

IDD

MREG

SR T Main regulator current variation

20 µs observation

window

–60

—

IMREGINT

CC D Main regulator current

consumption

IMREG = 300 mA

—

3.5

IMREG = 0 mA

—

2.2

SPC574K72E5 Datasheet(PDF) 72 Page - STMicroelectronics

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