SPC574K72E5 datasheet(40/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

3.8

I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is

associated to a VDD/VSS supply pair.

Table 20 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment

should remain below the IAVGSEG maximum value.

In order to ensure device functionality, the sum of the dynamic and static currents of the I/O

on a single segment should remain below the IDYNSEG maximum value.

Pad mapping on each segment can be optimized using the pad usage information provided

in the I/O Signal Description table. The sum of all pad usage ratios within a segment should

remain below 100%.

t

TR20-80

Sum of transition time 20–

80% output pin VERY

STRONG configuration(8)

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

CL = 25 pF

——

VDD_HV_IO = 3.3 V ± 10%,

CL = 15 pF

(5)

——

t

SKEW_V

Difference between rise

and fall time at 20–80%

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

CL = 25 pF

(5)

0—1

TPHL/PLH

Propagation delay

CL = 25 pF,

4.5 V < VDD_HV_IO < 5.9 V

——

CL = 25 pF,

3.0 V < VDD_HV_IO < 3.6 V

—

10.5

CL = 50 pF, 

4.5 V < VDD_HV_IO < 5.9 V

——

CL = 50 pF, 

3.0 V < VDD_HV_IO < 3.6 V

——

IDCMAX_VS CC

Maximum DC current

—

Refer to FlexRay section for parameter dedicated to this interface.

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0.

All values need to be confirmed during device validation.

Only available on the VDD_HV_IO_JTAG and VDD_HV_IO_FLEX segments.

CL is the sum of external capacitance. Add device and package capacitances (CIN, defined in Table 14: I/O input DC

electrical characteristics) to calculate total signal capacitance (CTOT = CL + CIN).

20–80% transition time as per FlexRay standard.

TTL transition time as for Ethernet standard.

For specification per Electrical Physical Layer Specification 3.0.1, see the dCCTxDRISE25+dCCTxDFALL25 (Sum of Rise and

Fall time of TxD signal at the output pin) specification in Table 58: TxD output characteristics in Section 3.17.4.2: TxD.

Table 19. VERY STRONG configuration output buffer electrical characteristics(1)(Continued)

Symbol

Parameter

Conditions(2)

Value(3)

Unit

Min

Typ

Max

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