SPC574K72E5 datasheet(75/127 Pages) STMICROELECTRONICS

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SPC574Kxx

Electrical characteristics

126

3.15.4

Power up/down sequencing

The following table shows the constraints and relationships for the different power supplies.

tVDASSERT

Voltage detector threshold

crossing assertion

—0.1

—

µs

tVDRELEASE CC

Voltage detector threshold

crossing de-assertion

—5

—

µs

For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR drop

is estimated by multiplying the supply current by 0.5

.

VPORUP_LV and VPORUP_HV threshold are untrimmed values before completion of the power-up sequence. All other

LVD/HVD thresholds are provided after trimming.

Assume all of LVDs on LV supplies disabled.

LV internal supply levels are measured on device internal supply grid after internal voltage drop.

LVD is released after tVDRELEASE temporization when upper threshold is crossed, LVD is asserted tVDASSERT after detection

when lower threshold is crossed.

This is combination of LVD108_C, P, and F. Min is from min value of LVD108_F, and P which is the lowest one. Max is the

max value of LVD108_C which is the highest one of three.

LV external supply levels are measured on the die side of the package bond wire after package voltage drop.

HVD is released after tVDRELEASE temporization when lower threshold is crossed, HVD is asserted tVDASSERT after

detection when upper threshold is crossed. HVD140 does not cause reset.

This supply also needs to be below 5472 mV (untrimmed HVD600 min).

10. Untrimmed LVD300_A will be asserted first on power down.

11. Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage supply.

When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not shorted

(VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.

Table 37. Voltage monitor electrical characteristics(1)(Continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

Table 38. Device supply relation during power-up/power-down sequence

Supply 2(1)

VDD_LV

VDD_HV_IO_JTAG/

VDD_HV_IO_FLEX

VDD_HV_IO VDD_HV_ADV VDD_HV_ADR

ALTREFn(2)

VDD_LV

VDD_HV_IO_JTAG/

VDD_HV_IO_FLEX

VDD_HV_IO

VDD_HV_ADV

VDD_HV_ADR

5 mA

ALTREFn

10 mA(3)

Red cells: Supply 1 (row) can exceed Supply 2 (column), granted that external circuitry ensures current flowing from

supply1 is less than absolute maximum rating current value provided.

ALTREFn are the alternate references for the ADC that can be used in place of the default reference (VDD_HV_ADR_*). They

are SARB.ALTREF and SAR2.ALTREF.

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