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SPC574K72E5 Datasheet(PDF) 89 Page - STMicroelectronics |
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SPC574K72E5 Datasheet(HTML) 89 Page - STMicroelectronics |
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89 / 127 page  DocID023601 Rev 5 89/127 SPC574Kxx Electrical characteristics 126 4tSDC CC D SCK duty cycle(7) SCK drive strength Very strong 0 pF 1/ 2tSCK – 2 1/ 2tSCK + 2 ns Strong 0 pF 1/ 2tSCK – 2 1/ 2tSCK + 2 Medium 0 pF 1/ 2tSCK – 5 1/ 2tSCK + 5 PCS strobe timing 5tPCSC CC D PCSx to PCSS time(8) PCS and PCSS drive strength Strong 25 pF 16.0 —ns 6tPASC CC D PCSS to PCSx time(8) PCS and PCSS drive strength Strong 25 pF 16.0 —ns SIN setup time 7tSUI CC D SIN setup time to SCK(9) SCK drive strength Very strong 25 pF 25.0 — ns Strong 50 pF 31.0 — Medium 50 pF 52.0 — SIN hold time 8tHI CC D SIN hold time from SCK(9) SCK drive strength Very strong 0 pF –1.0 — ns Strong 0 pF –1.0 — Medium 0 pF –1.0 — SOUT data valid time (after SCK edge) 9tSUO CC D SOUT data valid time from SCK(10) SOUT and SCK drive strength Very strong 25 pF — 7.0 ns Strong 50 pF — 8.0 Medium 50 pF — 16.0 SOUT data hold time (after SCK edge) 10 tHO CC D SOUT data hold time after SCK(10) SOUT and SCK drive strength Very strong 25 pF –7.7 — ns Strong 50 pF –11.0 — Medium 50 pF –15.0 — 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. All timing values for output signals in this table are measured to 50% of the output voltage. 3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. Table 48. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1(1)(Continued) # Symbol C Characteristic Condition Value(2) Unit Pad drive(3) Load (CL)Min Max |
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