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SPC574K72E5 Datasheet(PDF) 39 Page - STMicroelectronics

Part # SPC574K72E5
Description  32-bit Power Architecture based MCU for automotive applications
PDF  127 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC574K72E5 Datasheet(HTML) 39 Page - STMicroelectronics

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SPC574Kxx
Electrical characteristics
126
Table 19 shows the VERY STRONG configuration output buffer electrical characteristics.
3.
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 14) are to be added to
calculate total signal capacitance (CTOT = CL + CIN).
4.
Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.
5.
Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_FLEX segment when VSIO[VSIO_IF] = 0
Table 19. VERY STRONG configuration output buffer electrical characteristics(1)
Symbol
C
Parameter
Conditions(2)
Value(3)
Unit
Min
Typ
Max
ROH_V
CC
P
PMOS output impedance
VERY STRONG
configuration
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
IOH = 8 mA
——
60
CVDD_HV_IO = 3.3 V ± 10%,
VSIO[VSIO_xx] = 0,
IOH = 7 mA
(4)
——
85
ROL_V
CC
P
NMOS output impedance
VERY STRONG
configuration
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
IOL = 8 mA
——
60
CVDD_HV_IO = 3.3 V ± 10%,
VSIO[VSIO_xx] = 0,
IOL = 7 mA
(4)
——
85
fMAX_V
CC
T
Output frequency
VERY STRONG
configuration
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 25 pF
(5)
——
50
MHz
VDD_HV_IO = 3.3 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 15 pF
(4),(5)
——
50
tTR_V
CC
T
10–90% threshold
transition time output pin
VERY STRONG
configuration
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 25 pF
(5)
1—
5.3
ns
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 50 pF
(5)
2.5
—
12
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 200 pF
(5)
11
—
45
tTR20-80
CC
D
20–80% threshold
transition time(6) output pin
VERY STRONG
configuration
VDD_HV_IO = 5.0 V ± 10%,
VSIO[VSIO_xx] = 1,
CL = 25 pF
(5)
0.8
—
4
ns
VDD_HV_IO = 3.3 V ± 10%,
CL = 15 pF
(5)
1—5
tTRTTL
CC
D
TTL threshold transition
time(7) for output pin in
VERY STRONG
configuration
VDD_HV_IO = 3.3 V ± 10%,
CL = 25 pF
(5)
1—5
ns



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