SPC574K72E5 datasheet(46/127 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Kxx

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DocID023601 Rev 5

3.10

Oscillator and FMPLL

3.10.1

FMPLL

Two frequency-modulated phase-locked loop (FMPLL) modules, the Reference PLL (PLL0)

and the System PLL (PLL1) generate the system and auxiliary clocks from the main oscillator

driver.

Figure 10. PLL integration

PLL0

PLL1

IRCOSC

XOSC

PLL1_PHI

PLL0_PHI1

PLL0_PHI

Table 22. PLL0 electrical characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

fPLL0IN

—

PLL0 input clock(1),(2)

—8

—

MHz



PLL0IN

—

PLL0 input clock duty

cycle(1)

—40

—

fPLL0VCO

PLL0 VCO frequency

—

600

—

1250

MHz

fPLL0PHI

PLL0 clock output

frequency on PHI

—

400

MHz

fPLL0PHI1

PLL0 clock output

frequency on PHI1

——

—

MHz

tPLL0LOCK

PLL0 lock time

—

110

µs



PLL0PHI0SPJIT CC

PLL0_PHI0 single period

jitter

fPLL0IN = 20 MHz

(resonator)

fPLL0PHI0 = 400 MHz, 6-

sigma pk-pk

—

200



PLL0PHI1SPJIT CC

PLL0_PHI1 single period

jitter

fPLL0IN = 20 MHz

(resonator)

fPLL0PHI1 = 40MHz, 6-

sigma pk-pk

—

300(3)

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